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document # sram143 rev a revised october 2011 p3c1256l low power 32k x 8 static cmos ram features v cc current (commercial/industrial) operating: 70ma/85ma cmos standby: 100a/100a access times 55/70/85 wide range power supply: 2.7v to 3.6v easy memory expansion using ce and oe inputs common data i/o three-state outputs fully ttl compatible inputs and outputs advanced cmos technology automatic power down packages 28-pin 600 mil dip 28-pin 330 mil sop 28-pin tsop functional block diagram pin config urations dip (p6), sop (s11-3) top view description the p3c1256l is a 262,144-bit low power cmos static ram organized as 32kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates with a wide range power supply (2.7v to 3.6v). access times of 55 ns and 70 ns are available. cmos is utilized to reduce power consumption to a low level. the p3c1256l device provides asynchronous operation with matching access and cycle times. memory locations are specifed on address pins a 0 to a 14 . reading is accom - plished by device selection ( ce and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low.
p3c1256l - 32k x 8 static cmos ram page 2 document # sram143 rev a dc electrical characteristics (over recommended operating temperature & supply voltage) (2) maximum r atings (1) recommen ded operating temperature and suppl y volta ge sym parameter test conditions min max unit v oh output high voltage (i/o 0 - i/o 7 ) i oh = -1ma, v cc = 3.0v 2.4 v v ol output low voltage (i/o 0 - i/o 7 ) i ol = 2.1ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage -0.5 (3) 0.8 v i li input leakage current gnd v in v cc com -2 +2 a ind -5 +5 mil i lo output leakage current gnd v out v cc ce = v ih com -2 +2 a ind -5 +5 mil i sb v cc current ttl standby current (ttl input levels) v cc = 3.6v, i out = 0 ma ce = v ih 3 ma i sb1 v cc current cmos standby current (cmos input levels) v cc = 3.6v, i out = 0 ma ce v cc - 0.2v 100 a n/a = not applicable sym parameter min max unit v cc supply voltage with respect to gnd -0.5 7.0 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 v cc + 0.5 v t a operating ambient temperature -55 125 c s tg storage temperature -65 150 c i out output current into low outputs 25 ma i lat latch-up current > 200 ma temperature range (ambient) supply voltage commercial (0c to 70c) 2.7v v cc 3.6v industrial (-40c to 85c) 2.7v v cc 3.6v military (-55c to 125c) 2.7v v cc 3.6v
p3c1256l - 32k x 8 static cmos ram page 3 document # sram143 rev a capacita nces (4) (v cc = 3.3v, t a = 25c, f = 1.0mhz) symbol parameter test conditions max unit c in input capacitance v in =0v 7 pf c out output capacitance v out =0v 9 pf power dissipatio n characteristics vs. speed sym parameter temperature range * ** unit -55 -70 -85 -55 -70 -85 i cc dynamic operating current* commercial 70 70 70 15 15 15 ma industrial 85 85 85 25 25 25 ma military 100 100 100 35 35 35 ma * tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. the device is continuously enabled for writing, i.e. ce and we v il (max), oe is high. switching inputs are 0v and 3v. ** as above but @ f=1 mhz and v il /v ih = 0v/v cc . sym parameter -55 -70 -85 unit min max min max min max t rc read cycle time 55 70 85 ns t aa address access time 55 70 85 ns t ac chip enable access time 55 70 85 ns t oh output hold from address change 5 5 5 ns t lz chip enable to output in low z 5 5 5 ns t hz chip disable to output in high z 20 25 30 ns t oe output enable low to data valid 30 35 40 ns t olz output enable low to low z 5 5 5 ns t ohz output enable high to high z 20 25 30 ns t pu chip enable to power up time 0 0 0 ns t pd chip disable to power down time 55 70 85 ns ac electrical characteristicsread c ycle (over recommended operating temperature & supply voltage)
p3c1256l - 32k x 8 static cmos ram page 4 document # sram143 rev a timing waveform of read cycle no. 1 ( oe controlled) (5) timing waveform of read cycle no. 2 (address controlled) (5,6) notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C3.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address. timing waveform of read cycle no. 3 (address controlled) (5,7)
p3c1256l - 32k x 8 static cmos ram page 5 document # sram143 rev a ac characteristicswrite cycle (over recommended operating temperature & supply voltage) symbol parameter -55 -70 -85 unit min max min max min max t wc write cycle time 55 70 85 ns t cw chip enable time to end of write 50 60 75 ns t aw address valid to end of write 50 60 75 ns t as address setup time 0 0 0 ns t wp write pulse width 40 50 60 ns t ah address hold time 0 0 0 ns t dw data valid to end of write 25 30 35 ns t dh data hold time 0 0 0 ns t wz write enable to output in high z 25 30 35 ns t ow output active from end of write 5 5 5 ns timing waveform of write cycle no. 1 ( we controlled) (10,11) notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the frst transitioning address.
p3c1256l - 32k x 8 static cmos ram page 6 document # sram143 rev a ac test conditions truth table timing w aveform of write cycle no. 2 ( ce controlled) (10) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce oe we i/o power standby h x x high z standby standby x x x high z standby d out disabled l h h high z active read l l h d out active write l x l high z active figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the high speed of the p3c1256l, care must be taken when testing this device; an inadequate setup can cause a normal function - ing part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.77v (thevenin voltage) at the comparator input, and a 589? resistor must be used in series with d out to match 639? (thevenin resistance).
p3c1256l - 32k x 8 static cmos ram page 7 document # sram143 rev a data rete ntion characteristics data rete ntion waveform sym parameter test conditions min typ.* v cc = max v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current ce v cc - 0.2v, v in v cc - 0.2v or v in 0.2v 10 15 80 120 a t cdr chip deselect to data reten - tion time 0 ns t r ? operation recovery time t rc ns * ta = +25c t rc = read cycle time ? = this parameter is guaranteed but not tested.
p3c1256l - 32k x 8 static cmos ram page 8 document # sram143 rev a ordering in formation
p3c1256l - 32k x 8 static cmos ram page 9 document # sram143 rev a pkg # p6 # pins 28 (600 mil) symbol min max a 0.090 0.200 a1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 c 0.008 0.012 d 1.380 1.430 e 0.485 0.550 e1 0.600 0.625 e 0.100 bsc eb 0.600 typ l 0.100 0.180 0 15 plastic dual i n-lin e package soic/sop small outli n e ic package pkg # s11-3 # pins 28 (330 mil) symbol min max a 0.094 0.120 a1 0.002 0.014 b 0.014 0.020 c 0.008 0.012 d 0.702 0.728 e 0.050 bsc e 0.291 0.340 h 0.463 0.477 h 0.010 0.029 l 0.020 0.050 0 8
p3c1256l - 32k x 8 static cmos ram page 10 document # sram143 rev a pkg # t1 # pins 28 symbol min max a 0.039 0.047 a 2 0.036 0.040 b 0.007 0.011 d 0.461 0.469 e 0.311 0.319 e 0.022 bsc h d 0.520 0.535 tsop thi n small outlin e package
p3c1256l - 32k x 8 static cmos ram page 11 document # sram143 rev a revisions document number sram143 document title p3c1256l low power 32k x 8 static cmos ram rev issue date origin ator description of change or jul-2011 jdb new data sheet a oct-2011 jdb added wide range power supply

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